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TC74HC40105AP/AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC40105AP,TC74HC40105AF
4 Bit x 16 Word FIFO Register
The TC74HC40105A is a high speed CMOS 4 bit x 16 word first-in, first-out (FIFO) Strage Register fabricated with silicon gate C2MOS technology. It achieves the high speed operation while maintaining the CMOS low power dissipation. The device is capable of handling 16 four-bit words and it is possible to handle the input and output data at different shifting rates. When the DATA-IN-READY (DIR) is high, data is written into the registers by a low to high transition of the SHIFT IN (SI) input. And when DATA-OUT-READY (DOR) is high, data is read out of the registers by a high to low transition of the SHIFT OUT ( SO ) input. If the MASTER RESET (MR) is high, the DIR goes high and DOR goes low. The data in the internal registers are not changed but are declared invalid. The TC74HC40105A can be cascaded to form longer registers or wider words. The DATA OUTPUTs (Qn) are 3-State Outputs. When OUTPUT ENABLE ( OE ) is held high, the Qn's are in high impedance state. All inputs are equipped with protection circuits against static discharge or transient excess voltage.
TC74HC40105AP
TC74HC40105AF
Weight DIP16-P-300-2.54A SOP16-P-300-1.27A
: 1.00 g (typ.) : 0.18 g (typ.)
Features
* * * * *
High speed: fmax 25 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 4 A (max) at Ta = 25C High noise immunity: VNIH = VNIL = 28% VCC (min) Output drive capability: 10 LSTTL loads for DIR, DOR 15 LSTTL loads for Q0 to Q3 Symmetrical output impedance: |IOH| = IOL = 4 mA (min) for DIR, DOR |IOH| = IOL = 6 mA (min) for Q0 to Q3 Balanced propagation delays: tpLH - tpHL Wide operating voltage range: VCC (opr) = 2 to 6 V
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TC74HC40105AP/AF
Pin Assignment
IEC Logic Symbol
System Diagram
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Timing Chart
Z: High impedance
Block Diagram
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Functional Description
(1) Writing data Data can be written into the FIFO whenever DIR is high and a low to high transition occurs on the SI pin. DIR will toggle momentarily until the data has been transferred to the second word register. SI must be toggled before the next 4-bit word can be written. The first and subsequent words will automatically ripple to the output end of the device even if there is not a full 16 words of input data. When all 16 words are filled with data, DIR will go low and additional data cannot be written into the device. Reading data When a data word appears in the sixteenth data register (just before the output buffer), DOR goes high and, if OE is low, data can be output on the high to low transition of SO . The data remaining in the registers now ripples to the next higher word position opening the first word position for new data. DIR goes high and additional data can be written in. During the output of data, DOR toggles momentarily after each read. When the data registers become empty, DOR goes low and SO is ignored. Master rest When a high is input to MR, the internal control logic is initialized. This causes DIR to go high and DOR to go low. The contents of the data registers are not changed, but are invalid and will be written over when the first word is loaded. Cascading The TC74HC40105A can be cascaded to form longer registers simply by connecting DOR of the first device to SI of the second and DIR of the second device to SO of the first. Additional devices may be cascaded by repeating the above. Of course, the Qn outputs of the first device must be connected to the Dn inputs of the second. In this mode, an MR pulse must be applied after the supply voltage is turned on. For words wider than 4-bits, the DIR and DOR outputs from each FIFO must be ANDed respectively and the SI and SO inputs must each be paralleled.
(2)
(3)
(4)
Absolute Maximum Ratings (Note 1)
Characteristics Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature (DIR, DOR) (Q0 to Q3) Symbol VCC VIN VOUT IIK IOK IOUT ICC PD Tstg Rating -0.5 to 7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 25 35 75 500 (DIP) (Note 2)/180 (SOP) -65 to 150 Unit V V V mA mA mA mA mW C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = -40 to 65C. From Ta = 65 to 85C a derating factor of -10 mW/C shall be applied until 300 mW.
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Operating Ranges (Note)
Characteristics Supply voltage Input voltage Output voltage Operating temperature Symbol VCC VIN VOUT Topr Rating 2 to 6 0 to VCC 0 to VCC -40 to 85 0 to 1000 (VCC = 2.0 V) Input rise and fall time tr, tf 0 to 500 (VCC = 4.5 V) 0 to 400 (VCC = 6.0 V) ns Unit V V V C
Note:
The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND.
Electrical Characteristics
DC Characteristics
Test Condition Characteristics Symbol VCC (V) 2.0 High-level input voltage VIH 4.5 6.0 2.0 Low-level input voltage VIL 4.5 6.0 2.0 VIN = VIH or VIL High-level output voltage VOH (DIR DOR) (Q0 to Q3) IOH = -20 A IOH = -4 mA IOH = -5.2 mA IOH = -6 mA IOH = -7.8 mA IOL = 20 A IOL = 4 mA IOL = 5.2 mA IOL = 6 mA IOL = 7.8 mA 4.5 6.0 4.5 6.0 4.5 6.0 2.0 VIN = VIH or VIL Low-level output voltage VOL (DIR DOR) (Q0 to Q3) 3-state output off-state current Input leakage current Quiescent supply current IOZ IIN ICC VIN = VIH or VIL VOUT = VCC or GND VIN = VCC or GND VIN = VCC or GND 4.5 6.0 4.5 6.0 4.5 6.0 6.0 6.0 6.0 Min 1.50 3.15 4.20 1.9 4.4 5.9 4.18 5.68 4.18 5.68 Ta = 25C Typ. 2.0 4.5 6.0 4.31 5.80 4.31 5.80 0.0 0.0 0.0 0.17 0.18 0.17 0.18 Max 0.50 1.35 1.80 0.1 0.1 0.1 0.26 0.26 0.26 0.26 0.5 0.1 4.0 Ta = -40 to 85C Min 1.50 3.15 4.20 1.9 4.4 5.9 4.13 5.63 4.13 5.63 Max 0.50 1.35 1.80 0.1 0.1 0.1 0.33 0.33 0.33 0.33 5.0 1.0 40.0 A A A V V V V Unit
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Timing Requirements (input: tr = tf = 6 ns)
Characteristics Symbol Test Condition VCC (V) Minimum pulse width (SI) tW (L) tW (H) 2.0 4.5 6.0 Ta = 25C Typ. Limit 75 15 13 Ta = -40 to 85C Limit 95 19 16 ns Unit
Minimum pulse width ( SO )
tW (L) tW (H)
2.0
75 15 13 75 15 13 0 0 0 100 20 17 50 10 9 3 15 18
95 19 16 95 19 16 0 0 0 125 25 21 65 13 11 2.4 12 13 MHz ns ns ns ns ns
4.5 6.0 2.0
Minimum pulse width (MR)
tW (L) tW (H)
4.5 6.0 2.0
Minimum set-up time (DATA-SI)
ts
4.5 6.0 2.0
Minimum hold time (DATA-SI)
th
4.5 6.0 2.0
Minimum removal time (MR-SI)
trem
4.5 6.0 2.0
Clock frequency
f
4.5 6.0
AC Characteristics (CL = 15 pF, VCC = 5 V, Ta = 25C, input: tr = tf = 6 ns)
Characteristics Output transition time (DIR, DOR) Propagation delay time ( SO , MR-DOR) Propagation delay time ( SO -DIR) Propagation delay time (SI-DOR) Propagation delay time (SI-DIR) Propagation delay time (MR-DIR) Symbol tTLH tTHL tpHL Test Condition
Min
Typ. 4
Max 8
Unit ns
22
39
ns
tpLH
242
365
ns
tpLH
187
300
ns
tpHL tpLH tpHL
22
35
ns
25
39
ns
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AC Characteristics (input: tr = tf = 6 ns)
Test Condition Characteristics Symbol CL (pF)
Ta = 25C VCC (V) 2.0 50 4.5 6.0 2.0 Min

Ta = -40 to 85C Max 60 12 10 75 15 13 225 45 38 2000 400 340 1650 330 280 200 40 34 400 80 68 440 88 75 1500 300 255 1540 308 262 225 45 38 125 25 21 165 33 28 125 25 21 Min

Unit
Typ. 21 7 6 24 8 7 84 28 24 798 266 226 624 208 177 78 26 22 156 52 44 171 57 48 612 204 173 627 209 178 87 29 25 45 15 13 60 20 17 32 16 14
Max 75 15 13 95 19 16 280 56 48 2500 500 425 2060 412 350 250 50 43 500 100 85 550 110 94 1875 375 319 1925 385 327 280 56 48 155 31 26 205 41 35 155 31 26 ns ns ns ns ns ns ns ns ns ns ns
Output transition time (Q0 to Q3)
tTLH tTHL
Output transition time (DIR, DOR) Propagation delay time ( SO , MR-DOR) Propagation delay time ( SO -DIR) Propagation delay time (SI-DOR) Propagation delay time (SI-DIR)
tTLH tTHL
50
4.5 6.0 2.0
tpHL
50
4.5 6.0 2.0
tpLH
50
4.5 6.0 2.0
tpLH
50
4.5 6.0 2.0
tpHL
50
4.5 6.0 2.0
50 Propagation delay time ( SO -Qn) tpLH tpHL
4.5 6.0 2.0
150
4.5 6.0 2.0
50 Propagation delay time (SI-Qn) tpLH tpHL
4.5 6.0 2.0
150
4.5 6.0
Propagation delay time (MR-DIR)
tpLH tpHL
2.0
50
4.5 6.0 2.0
50 Output enable time tpZL tpZH RL = 1 k 150
4.5 6.0 2.0 4.5 6.0
Output disable time
tpLZ tpHZ
2.0 RL = 1 k 50 4.5 6.0
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Test Condition Characteristics Symbol CL (pF) 50 Maximum clock frequency fmax
Ta = 25C VCC (V) 2.0 4.5 6.0 2.0 Min 3 15 18 2.6 13 15

Ta = -40 to 85C Max

Unit
Typ. 7 22 26 6 20 24 95 25 21 95 25 21 5 10 300
Min 2.4 12 14 2 10 12

Max

MHz
150
4.5 6.0
Output pulse width (DIR)
tw (H) tw (L)
2.0
50
4.5 6.0 2.0
ns
Output pulse width (DOR) Input capacitance Output capacitance Power dissipation capacitance
tw (H) tw (L) CIN COUT CPD
50
4.5 6.0
ns

10

10

pF pF pF
(Note)
Note:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPDVCCfIN + ICC
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Package Dimensions
Weight: 1.00 g (typ.)
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Package Dimensions
Weight: 0.18 g (typ.)
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TC74HC40105AP/AF
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice.
20070701-EN GENERAL
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer's own risk. * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. * Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.
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